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Synchronous programming languages
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#	Item
31	Binarization of Synchronous Context-Free Grammars Liang Huang∗ USC/Information Science Institute Hao Zhang∗∗ Add to Reading List Source URL: www.aclweb.org Language: English - Date: 2010-06-14 18:57:01 Programming language implementation CYK algorithm Formal grammar Context-free grammar Earley parser Parsing Parse tree Stochastic context-free grammar Terminal and nonterminal symbols Formal languages Linguistics Science
32	Streaming Models of Computation in The Ptolemy Project Edward A. Lee Professor UC Berkeley Workshop on Streaming Systems, Add to Reading List Source URL: ptolemy.eecs.berkeley.edu Language: English - Date: 2003-09-03 14:12:53 Formal methods Hardware description languages Synchronous programming languages Computer architecture Dataflow Ptolemy Project Kahn process networks SIGNAL Parallel computing Computing Software engineering Models of computation
33	Laboratoire VERIMAG UMR 5104 Directeur: Nicolas Halbwachs Campagne d’´ evaluation 2011–2015 Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2010-02-11 10:51:36 Validity Science Theoretical computer science Hardware description languages Technology Synchronous programming language Lustre Joseph Sifakis Verification Formal methods Systems engineering Pharmaceutical industry
34	VERIMAG A LEADING RESEARCH CENTRE IN EMBEDDED SYSTEMS since 1992 VERIMAG Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2012-12-06 03:52:13 Esterel Technologies Electronic engineering Joseph Sifakis Lustre Computing Wireless sensor network Technology Model checking Formal methods Hardware description languages Synchronous programming languages
35	Taxys = Esterel + Kronos A tool for verifying real-time properties of embedded systems 1 V. Bertin Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2012-12-31 04:25:31 Software engineering Computer programming Esterel SIGNAL Model checking Embedded system Scheduling Porting Operating system Hardware description languages Synchronous programming languages Computing
36	Building Models of Real-Time Systems from Application Software JOSEPH SIFAKIS, STAVROS TRIPAKIS, ASSOCIATE MEMBER, IEEE, AND SERGIO YOVINE Invited Paper We present a methodology for building timed models of real-time Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2012-12-31 04:25:32 Formal methods Concurrent computing Software development Electronic engineering SIGNAL Esterel Real-time computing Actor model Model checking Computing Hardware description languages Synchronous programming languages
37	✲ Towards Validated Real-Time Software✲ Valérie BERTIN†, Michel POIZE, Jacques PULOU Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2012-12-31 04:25:30 Models of computation Model checkers Esterel Automata theory Model checking SIGNAL Theoretical computer science Uppaal Model Checker Computing Hardware description languages Synchronous programming languages Software engineering
38	TAXYS : a Tool for the Development and Verification of Real-Time Embedded Systems⋆ Etienne CLOSSE1 , Michel POIZE1 , Jacques PULOU1 , Joseph SIFAKIS2 , Patrick VENIER1 , Daniel Weil1 , and Sergio YOVINE2 1 Add to Reading List Source URL: www-verimag.imag.fr Language: English - Date: 2012-12-31 04:25:31 Model checking Software engineering Embedded system Real-time computing Computing Electronics Esterel Technologies SIGNAL Hardware description languages Synchronous programming languages Esterel
39	Home Page Title Page Globally Asynchronous Locally Synchronous Systems (GALS): Add to Reading List Source URL: www.cse.iitb.ac.in Language: English - Date: 2004-06-13 11:56:27 Synchronous programming languages Electronic engineering Concurrent computing SIGNAL Finite-state machine Globally asynchronous locally synchronous Ada Thread Esterel Computing Software engineering Hardware description languages
40 $Electronic Communications of the EASST No \volume defined! No \volumetitle defined! Verification of Railway Interlockings in Scade$	Electronic Communications of the EASST No \volume defined! No \volumetitle defined! Verification of Railway Interlockings in Scade Add to Reading List Source URL: www-compsci.swan.ac.uk Language: English - Date: 2012-10-25 14:18:24 Science Formal methods Technology Formal sciences Esterel Technologies Railway signalling Lustre Interlocking Model checking Hardware description languages Synchronous programming languages Electronic engineering